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Operational Phases and Modes of Operation
Table 4-2. State transitions
Transition #
From
To
Trigger 1
STOPCR[FC] = 1, followed by STOP instruction; OR
2
3
4
5
6
7
8
9
RUN
STOP FC
RUN
HALT
RESET
RUN
STOP NC
RESET
STOP SC
STOP FC
STOP SC
STOP FC
RUN
HALT
RUN
RUN
STOP NC
RUN
HALT
STOP FC
HALT
HALT
XCSR[ENBDM] =1, followed by STOP instruction (STOP SC and STOP NC are
emulated by STOP FC in debug mode.)
Any interrupt
When a BACKGROUND command is received through the BKGD/MS pin OR
when a HALT instruction is executed OR when encountering a BDM breakpoint.
GO instruction issued via BDM
De-assert all reset sources. Internal de-assert is subject to timing sequences
XCSR[ENBDM] = 0, STOPCR[NC] = 1, followed by STOP instruction
Any interrupt
BDM = 0 during POR (device must be unsecure)
Start of frame signal with STOPCR[A_EN] = 1
When a BACKGROUND command is received through the BKGD/MS pin
(XCSR[ENBDM] must equal one)
In debug mode, STOP SC is emulated by STOP FC .
1
Interrupts are subject to the limitations discussed in “Clock gating” on page 196 and “Peripheral Clock Enable Register 0 for
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
43
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